How To Create Solar Panel Pdf

Crystalline silicon solar cell (c‐Si) based technology has been recognized as the only environment‐friendly viable solution to replace traditional energy sources for power generation. It is a cost‐effective, renewable and long‐term sustainable energy source. The Si‐based technology has a market growth of almost 20‐30% and is projected to attain an energy share of ~100 giga watt (GW) per year in the current fiscal year, 2020. There have been constant efforts in reducing manufacturing cost of solar panel technology, which is about three‐four times higher in comparison to traditional carbon‐ based fuels. In the manufacturing domain, fabrication of three basic c‐Si solar cell configurations can be utilized, which are differentiated in the manner of generation of electron‐hole (E‐H) pairs on exposure to sunlight. The generation of electricity by impinging light on a semiconductor material requires production of electrons and holes such that electrons in the valence band become free and jump to the conduction band by absorbing energy. Thus, jumping of highly energetic electrons to different material generates an electromotive force (EMF) converting light energy into electrical signals. This is known as the photovoltaic (PV) effect. This chapter is an effort to outline fabrication processes and manufacturing methodologies for commercial production of large area PV modules as an alternative green source of energy.

Figures - uploaded by Sudhanshu Dwivedi

Author content

All figure content in this area was uploaded by Sudhanshu Dwivedi

Content may be subject to copyright.

Discover the world's research

20+ million members
135+ million publications
700k+ research projects

Join for free

Fabrication and Manufacturing Process of Solar Cell

S. Dwivedi*

S.S. Jain Subodh P.G. (Autonomous) College, Jaipur, India

*E-mail : sudhanshu.dwivedi@gmail.com

Abstract

Crystalline silicon solar cell (c-Si) based technology has been recognized as the only

environment-friendly viable solution to replace traditional energy sources for power

generation. It is a cost-effective, renewable and long-term sustainable energy source. The Si-

based technology has a market growth of almost 20-30% and is projected to attain an energy

share of ~100 giga watt (GW) per year in the current fiscal year, 2020. There have been

constant efforts in reducing manufacturing cost of solar panel technology, which is about

three-four times higher in comparison to traditional carbon-based fuels. In the manufacturing

domain, fabrication of three basic c-Si solar cell configurations can be utilized, which are

differentiated in the manner of generation of electron-hole (E-H) pairs on exposure to

sunlight. The generation of electricity by impinging light on a semiconductor material

requires production of electrons and holes such that electrons in the valence band become

free and jump to the conduction band by absorbing energy. Thus, jumping of highly energetic

electrons to different material generates an electromotive force (EMF) converting light

energy into electrical signals. This is known as the photovoltaic (PV) effect.

Si is widely used in PV cell technology since it is cheaper, abundant and Si-fabrication

technology is highly developed. First of all, polished Si wafers cut from highly pure industrial

grade Si boules are prepared which can be single-crystalline, polycrystalline or even

amorphous. After wafer procurement/fabrication, Si is doped selectively to make p -n

junctions and is processed to furnish a solar cell.

The manufacturing requirements of PV modules are cheaper cost of production and

further promotion of cost reduction by improved technology, greener manufacturing

methodology and no constraints in materials supply. For Si-based manufacturing technology,

supply chain is an important factor.

This chapter is an effort to outline fabrication processes and manufacturing

methodologies for commercial production of large area PV modules as an alternative green

source of energy.

1. INTRODUCTION

There has always been a surge to discover newer sources of energy which can be

effective alternatives for the orthodox sources of energy, such as, petrol, kerosene, wind

energy, thermal power generators [1,2]. In this quest, the sun is a natural huge source of

renewable green energy. It is noteworthy that the terrestrial soil is exposed to enormous

amount of solar energy as large as about ten thousand times of all the energy used around the

globe. The terrestrial hemisphere facing the sun receives power in excess of 50,000 terawatt

(TW) in each instance, which makes reception of enormous amount of energy possible [3].

Photovoltaics (PV) technology is a technology that relies on this infinite source of sunlight

and possesses inherent qualities of highly reduced service costs since sun provides free

energy, reliability, noiseless, minimum maintenance costs and readily installation features [4,

5].

As a matter of fact, thermonuclear fusion reactions happen non-stop at a temperature of

millions of degrees to generate huge energy in form of electromagnetic radiation of sunlight

[5,6]. The outer layer of the earth's atmosphere receives partial energy of the total energy

from the sun with a solar constant or an average irradiance of approximately 1367 Wm-2 with

a variation of ±3% [8]. This value of solar constant is dependent on the earth-to-sun distance

and on the solar activity. The solar constant is defined as the intensity of solar

electromagnetic radiation impinging on a unit surface area and is expressed in units of kWm-2

and is equal to the integral of the power of the individual frequencies in the spectrum of solar

radiation. The geometry of the sun-to-earth distance is displayed in Fig. 1 given below.

Figure 1. The above schematic shows the sun-earth geometry portraying distance

between the two celestial objects, diameters and the value of solar constant.

Solar irradiation is the integral of solar irradiance over a particular period of time

depicted by kWhm-2 and the radiation falling on the surface of the earth is actually diffuse

radiation [8]. Diffuse radiation is that part of light radiation striking the surface from whole of

the sky, while other radiations are the part reflected from the ground, and by surrounding

atmosphere. Different types of radiation received by a solar panel [9] are displayed in Fig. 2

as shown below.

Figure 2. The above figure portrays different radiations occurring from the sun which

consists of direct, diffuse and reflected radiations.

1.1 Introduction To Si Based Fabrication Technology

Photovoltaics technology is a green method of energy production which is based on

fabrication and manufacturing of solar cells on platform of Si wafers [9]. In this regard, it

is mandatory to know about the Si wafers. So, I will first discuss about the silicon and its

geometry as an integral component of the solar cell technology.

1.2 Introduction To Si Wafer

Silicon is a member of group 14 in the periodic table and is tetravalent metalloid,

semiconductor and brittle crystalline solid [10-12]. In 1906, silicon radio crystal detector

was developed as the first silicon based semiconductor device by Greenleaf Whittier

Pickard [13]. Russell Ohl discovered the nonlinear semiconductor devices, p -n junction,

and photovoltaic effect in the metalloid Si in 1940 [14]. During Second World War in

1941, radar microwave detectors were invented by developing techniques for production

of high quality germanium (Ge) and Si crystals [15]. William Shockley proposed a field-

effect amplifier based on Ge and Si in 1947, but, however, could not demonstrate the

prototype practically [16]. John Bardeen and Walter Brattain built the first working

device, point-contact transistor, in 1947 itself under the direction of William Shockley

only [17]. The first Si-based junction transistor was fabricated by the physical chemist

Morris Tanenbaum in 1954 at Bell Labs [18]. At Bell Labs in 1954, Carl Frosch and

Lincoln Derick found out by accident that it is possible to grow silicon-di-oxide (SiO2) on

Si wafers [19]. Later on, in 1958, they discovered that this as-grown SiO2 could be used

to mask Si surfaces during diffusion processes [19].

Si atom has fourteen electrons with electronic configuration 2,8,4 [1s 2, 2 s 2, 2 p 6, 3s 2,

3p 2 ] specifying that the number of valence electrons is 4 [10,11]. These valence electrons

occupy the 3s orbital and two 3p orbitals. In order to complete its octet and attain the

stable noble gas configuration of Argon (Ar), it can combine with other elements to form

SiX4 derivatives by forming sp 3 hybrid orbitals. In this case, the central Si atom taking

part in the bonding with other element shares an electron pair with each of the four atoms

of the bonding element.

Si and Ge crystallize in a diamond type cubic lattice structure which has the space-

lattice of face-centered cubic (fcc) [20, 21]. The atomic positions in the diamond-type

cubic lattice projected on a cubic platform are shown in Fig. 3. In a space-lattice of fcc-

type, two identical atoms at 000 and 



 form the primitive basis and are associated

with each point of the fcc lattice. In the above picturesque, fractions are the heights over

and above the base in units of a cube edge. In that case, points at 0 and 

 lie on the fcc

lattice, while those at 

 and 

 lie on the similar fcc lattice but are displaced along the

line of body diagonal by a magnitude of ¼ of its length. It is a known fact that the unit

cube of fcc lattice consists of 4 lattice points. As a result, diamond-type cubic lattice

contains 2 x 4 = 8 atoms. The diamond-type fcc lattice in Si displays tetrahedral bonding

characteristics [20, 21].

Figure 3. Schematic to show atomic positions in diamond-type cubic lattice.

Si is tetravalent and can be made p-type by adding dopants of boron (B), aluminium (Al)

& gallium (Ga), and addition of antimony (Sb), phosphorous (P) & arsenic (As) generates n-

type semiconductor material [10,11,20,21]. B and Ga possess only three valence electrons

and when they are mixed into the Si lattice, deficiency of an electron is created which is

termed as positively charged "vacancy" or "hole". Holes take part in conduction accepting an

electron from the neighbour and transitioning over the atoms. For making Si an n-type

semiconductor, Sb, P and As are added into the Si lattice in small quantities each having five

valence electrons, which creates an extra electron into the lattice. The availability of these

free electrons as a whole in the material creates a net flow of negatively charged carriers to

constitute current. Thus, addition of small amounts of either of two types of foreign atoms

changes Si crystal into a medium-type of conductor, which is semiconductor. Joining of two

types of semiconducting materials constitutes a device entailed as nonlinear semiconductor

diode [10,11,20-22]. Figure 4 shows a similar picture to portray the doping of two types of

foreign atoms in Si lattice.

Figure 4. Figure showing the doping of two types of foreign atoms of B (p-type) and P

(n -type) in Si to form semiconductor material with better conductivities.

1.3 Introduction To Diode Physics

When p-type and n-type junctions are combined to form p-n junctions, they possess a

characteristic called rectification [23-26]. Rectification is a property to allow flow of current

easily in one direction only [28,29]. In case of p-type material, the Fermi level (E F) is near the

valence band edge and is close to conduction band edge in n-type material as shown in Fig. 5.

In p-type configuration, holes are the majority carriers, while electrons are minority carriers.

Just the opposite happens in case of n-type materials in which electrons are majority carriers

and holes are minority carriers. Upon joining, large carrier concentration gradients happen at

the junction to cause carrier diffusion. Majority holes from the p-type are transported by

diffusion into the n-type semiconductor, while majority electrons from n-type semiconductor

are diffused towards the p-type. Holes continue to leave the side of p-type while electrons

SiSi

SiSiSiSi

Hole

Free

Electron

keep on moving from the side of n-type semiconductor till a saturation point is reached. In

this exercise of charge carrier transportation, a minor concentration of negative acceptor ions

Figure 5. Two semiconductor blocks of p-type and n-type before the formation of

junction and also showing position of Fermi level (E F) in the corresponding dopes

semiconductor material.

( 

) and positive donor ions ( 

) at the semiconductor junction remains unreacted. The

holes possess high mobility whereas acceptor atoms are permanently fixed in the

semiconductor lattice. Similar explanation follows in case of electrons leaving the n-type

semiconductor. A saturation point is attained after transportation of both types of charge

carriers to oppositely doped semiconductor blocks. The result of large concentration gradient

is that a part of the free electrons coming from donor impurity atoms migrates across the

semiconductor junction filling up holes in the p-type semiconductor material to produce

negative ions. On moving from n-type to p-type, positively charged donor ions (N D) are left

behind on the side of n-type. Similarly, holes coming from acceptor foreign atoms are

transported across the junction in an opposite direction having large number of free electrons.

The transport mechanism of holes and electrons across the p-n junction is called diffusion. As

a result, a space charge region is formed in the region combining p-type and n-type

semiconductor blocks. On the side of p-type block, a negative space charge region is formed,

while a positive space charge region is formed on the side of n-type semiconductor. The

constitution of this space charge region in the junction develops an electric field that is

directed from the holes towards the negative charge. The width of the p- and n-type layers is

dependent on the degree of heavy doping of each layer with acceptor impurity atoms ( N A)

and donor impurity atoms (N D), respectively. Fig. 6(a) below shows the space charge region

formed between the joining of two semiconductor blocks of p-type and n- type. The electric

field will be directed from positive charge towards the negative charge. Fig. 6(b) shows the

energy band diagram of a semiconducting p-n junction in thermal equilibrium. It needs to be

pointed out that the flow of charge carriers can be due to both drift and diffusion. It is

apparent from Fig. 6(b) that the hole drift current flows from right to left, while hole diffusion

current flows from left to right. The electron drift current flows from right to the left, while

electron diffusion current flows from left to right. Thus, the free charge carriers (electrons

and holes) produce current in two ways under the application of an electric field in a

semiconductor, i.e. by drift and diffusion. The passage of charge carriers under the effect of

an externally applied electric field generates a net current called as the drift current. In case of

p n

EC E C

spatial variation of concentrations of charge carriers in the semiconductor, charge carriers

have the tendency to move from regions of high concentration to regions of low

concentration called as the diffusion current. The spatial variation in charge carrier

concentration is called as the concentration gradient. Fig. 7 shows the current-voltage

characteristics of a typical p-n junction diode. When the junction is forward-biased (+ve

terminal of the battery connected to p-type having positive vacancies as majority carriers),

current (I) increases rapidly as a function of voltage (V). In case of application of reverse-

biasing (-ve terminal of the battery connected to p-type having positive vacancies as majority

carriers and +ve terminal of the battery connected to n-type having electrons majority

carriers), zero current flows initially virtually. A schematic of the two biasing regimes,

reverse (a) and forward (b) is shown in Fig. 7. Only small amount of current flows on

increasing the reverse potential through the battery terminals. At a critical value of the

reverse bias, the current suddenly increases which is called as the junction breakdown. The

diode response is achieved at relatively lower voltages (~1 V) in forward-biasing case. In

reverse-bias, the breakdown voltage or reverse critical voltage generally varies from few

volts to larger voltages. This is typically dependent on the amount of doping of foreign atoms

to form two types of semiconductor blocks or layers and different device parameters [10].

Figure 6. Space charge region formed in between the joining region of p-type and n-

type semiconductor blocks is shown in (a). The energy band diagram of a p-n

semiconductor junction in thermal equilibrium is shown in (b).

Figure 7. Current-voltage (I-V) characteristics of a semiconductor p-n junction.

Figure 8. The two biasing regimes of a diode, (a) reverse (b) forward, are shown in the

above schematic. In reverse bias, the diode acts as an open switch, while it acts as a

closed switch in case of forward bias.

In the reverse bias mode, the diode device acts as an open switch such that the positive

terminal of the source will attract free electrons from n-type and negative terminals will

attract holes from the p-type. As a result, concentration of ions in both the regions will

increase enhancing the width of the depletion region. In any case, minority carriers will enter

the depletion region and cross to other sides of the junction causing a small amount of current

called as reverse saturation current (I S). The term "saturation" here means that there will not

(a)

Reverse Bias

+ -

Forward Bias

h+ h + h +

e- e-

(b)

h+ h + h +

e- e-

-- ++

be any enhancement in the current on increasing the reverse bias potential. As can be seen

from Fig. 7, current change happens very quickly in small voltages initially reaching the

saturation current and dependency of the current on further changes in voltages is lost. At a

certain higher critical reverse voltage, usually after tens of voltages, a huge current is caused

in the opposite direction. On increasing the reverse voltage, it creates an electric field

impacting greater force on the electrons to move faster and an enhancement in kinetic energy

(K.E.) of electrons follows. This higher K.E. is transported to valence shell of electrons of

stable atoms by highly mobile electrons causing them to leave the atom and form the stream

of reverse current flow. The critical voltage at which this rapid change happens is called the

Zener voltage.

In forward biasing mode, an electric field forces free electrons in n-type block and holes

in p-type block towards the depletion region. In this biasing, holes and free electrons

recombine with ions in the depletion region to reduce the width of the depletion region. On

increasing the forward voltage further, depletion region becomes thinner and a larger number

of majority carriers are able to pass through the barrier. It needs to be pointed out that no net

current flows in the diode in absence of an externally applied electric field.

1.3.1 Equilibrium Fermi Energy (E F )

In the state of thermal equilibrium, the individual hole and electron streams passing

through the barrier are ideally zero. The state of thermal equilibrium can be defined as the

steady-state condition at a given temperature when no externally applied field is present. In

this case, the net current density due to both drift and diffusion currents should be zero for

both holes and electrons. Thus, net current density for holes is given as [10,11,23,24],

 =  () +  ( )=  ……………(1)

= μ− 



= μ  

 

  −μ  

 = 0 …………….….…(2)

where, D p = 

 is the Einstein relation. Also,

The expression for hole concentration,

=  ⌊   ⌋/ ……………………………….(3)

Differentiating equation (3) with respect to x in the equilibrium condition (

 = np, p = n),



 = 

   

 −  

  …………….…………………..(4)

From equation (2) with the help of equation (4),

Jp = μ  

 

  −μ  



= μ  

  – μ  

   

 −  

 

= μ  

  − μ     

  + μ  

  



J p = μ 

 = 0 ……………………………(5)



 =  ……………………………………….(6)

Similarly, net current density for electrons is given as follows,

 =  (  )+  (  ) = ……………………..(7)

= μ + 



= μ 

 ……………………………………………..….…(8)

= 0 ………….………………………….………..….…(9)

Hence, 

 =  .……….………………………….………..….…(10)

It is apparent from equations (6) and (10) that the Fermi level ( E F) is not dependent on x and

remains uniform in whole of the semiconductor sample for zero net hole and electron

densities. This is also apparent from the band diagram as shown in Fig. 6(b). A typical space

charge distribution happens at the barrier due to uniform E F in the steady state. Considering

the 1D p-n junction when all donor and acceptor atoms are ionized, Poisson's equation for

electrostatic potential ψ and unique space charge distribution is given as follows [10,23,24],



 ≡ − 

 = −  

 = − 

 [   −   +−] ……………..(11)

The above situation is well represented in Fig. 9(a) in the energy band diagram of an abrupt

junction in the steady state. There is a unique space charge distribution at the semiconductor

junction. At distances far away from the barrier, net hole density is equal to the net electron

density such that the total space charge density is zero maintaining the charge neutrality. In

this case, from equation (11) [10,11,23,24],



 =  ………………............(12)

and,  −  +− = ……………………….(13)

In case of a p-type neutral region, N D = 0 and p >> n. Now, setting N D = n = 0 in equation

(13), we get, p = N A and putting it in equation (3) [10,11,23,24],

 = −

   

  ……………..(14)

Similarly, in case of n-type neutral region, N A = 0 and n >> p. Now, setting N A = p = 0 in

equation (13), we get, n = N D and putting in equation (3) [10,11,23,24],

 = −

   

  ……………..(15)

In the steady state, the total electrostatic potential difference between p-type and n-type

neutral regions is defined as the built-in-potential (V bi) and is given as follows [10,11,23,24],

  =  −  = 

   



 ……………(16)

Figure 9. The above figure (a) displays band diagram of an abrupt junction in steady

state and (b) displays an approximation of space charge distribution.

In between the neutral regions and semiconductor barrier, a narrow transition region exists

which has a width smaller in comparison to the width of the barrier or the depletion region.

This is true for regions existing on both sides of the depletion region. On neglecting the

transition regions in comparison to the depletion region, a nearby rectangular space charge

distribution is obtained as shown in Fig. 9(b) [10,23,24]. Here, x p and x n are the widths of the

depletion layer of p- and n-type blocks. In case of completely depleted region, the amount of

p and n dopants will be zero, and then from equation (11) [10,24],

qVbi

qψp

qψn

(a)



 ≡ − 

 = −  

 = − 

 [   −   +−] ……………..(11)



 = − 

 [   −  ]



 = 

 [   −   ] ……………..(17)

The physics of Poisson's equation lies in the fact that distribution of impurities can be

performed in form of shallow diffusion or low energy ion implantation or in form of deep

diffusions or high energy ion implantations [10,23,24]. The type of ion implantation

describes the doping profile according to the energy dose applied [30]. Shallow diffusion or

low energy ion implantation introduces foreign atoms at low depths to form abrupt p-n

junction. In this case, the doping concentration profile shows a rapid changeover between the

p-type and n-type regions. In case of high energy ion implantations, distribution of doping

profiles can be approximated almost linearly across the barrier called as linearly graded

junction.

Figure 10. Approximation of foreign atom doping profiles in semiconductor forming (a)

abrupt junction due to shallow diffusion and (b) linearly graded junction as a result of

deep diffusion.

In case of an abrupt junction, the free charge carriers are completely depleted such that

under the condition, -x p ≤ x < 0, equation (17) becomes [10],



 = +  

 ………………………..…(18)

In case of an abrupt junction, the free charge carriers are completely depleted such that

under the condition, 0 < x ≤ x n, equation (17) becomes [10],



 = −  

 ………………………..…(19)

-x p

xn x

ND - NA

(a)

ND - NA

(b)

For the space charge neutrality of the semiconductor as a whole,

NA xp = ND x n ……………………………….(20)

The total depletion layer width is given as follows,

t = x p + x n ………………………………....(21)

Figure 11. The schematic shows the electric field distribution and the width of the

depletion region or barrier. The area covered under the triangle shows the built-in-

potential (V bi). The width of the barrier is in reference to the width as shown in Fig. 9

displaying the space charge distribution.

The electric field distributed in the barrier can be obtained by integrating equations

(18) & (19) [10,11,23,24].

In case of -x p ≤ x < 0,  = −

 = −   (    )

 ……………………(22)

In case of 0 < x ≤ x n,  = −

 =   (    )

 ……………………(23)

Now, integrating equations (22) & (23) over the barrier gives V bi as follows,

  = ∫  



 = −∫  



  + ∫   



 ………...(24)

  =  



 +    



 = 

   …………………………………………..(25)

Hence, area covered under the shaded triangle in Fig. 11 corresponds to built-in-potential or

Vbi . Using above equations, Vbi as a function of the total width of depletion layer is given as,

ℎ    (  ) =  

     

    ……….………….(26)

The p-n junction circuit diagrams along with energy band diagrams for steady-state and

in case of forward- and reverse-biased states are shown in Fig. 12. Fig. 12(a) shows the p-n

junction circuit in the state of thermal equilibrium and the corresponding energy band

diagram is shown in Fig. 12(b) [10,11,23,24]. It is clear that the built-in-potential is V bi across

the junction formed by p- and n-blocks, while potential energy difference from p- to n-block

is qV bi. On applying positive potential V f so that the p-n junction is forward-biased, width of

-E Area Covered = V bi

Width of Depletion Region

the barrier is reduced due to the fact that the resultant electrostatic potential across the

semiconductor junction becomes V bi – V f as shown in Fig. 12(c) & (d). In case of reverse

biasing the p- and n-type blocks, the p-n junction barrier is reverse-biased so that the resultant

electrostatic potential at the junction becomes V bi + V r enhancing the overall width of the

depletion layer. This almost ceases the transport of charge carriers across the junction

because charge carriers cannot cross the wide barrier as shown in Fig. 12(e) & (f).

Figure 12. Schematic representations of barrier width and corresponding band energy

diagrams of a p-n junction in (a) steady-state equilibrium condition and (b) related

band energy diagram, (c) forward biasing showing forward current ( I) and voltage V f

and (d) associated band energy diagram, (e) reverse biased diode circuit showing

reverse current (I r) and voltage (Vr) and (f) correlated energy band diagram. It is clear

that the width of depletion layer decreases in forward-biased circuit in (c) so that

charge-carriers cross the barrier easily, while it increases in reverse-biased circuit in (e)

which makes transportation of charge-carriers across the barrier difficult.

Depletion Capacitance

Accumulation of holes and electrons at the junction of p- and n-type blocks or layers

creates a capacitive effect at the barrier. This depletion layer capacitancse can be defined as

= 

 per unit area [10,31]. Here, C is the capacitance, dq is the differential change in

charge per unit area with respect to differential change in the applied voltage dV. A p-n

junction with an arbitrary impurity profile is shown in Fig. 13(a), while 13(b) & 13(c) show

the profile of change in space charge as a function of change of the applied bias and the

corresponding change in the electric field distribution. When the applied bias on the side of n-

type block is increased by a differential voltage dV such that the total applied bias becomes V

+ dV, an enhancement in the region enclosed by charge carriers and the associated electric

field distribution profile can be seen as given in Fig. 13(c) within the barrier width (t). The

differential change in charge dq is shown by the green coloured rectangular blocks on both

sides of the barrier in Fig. 13(b) maintaining overall charge neutrality. The differential

positive change in electric field is given by  = 

 . The associated differential change can

Figure 13. Schematic shows an arbitrarily profile of dopants when reversed bias as

shown in (a). Schematics (b) and (c) show the change in space charge distribution and

electric field profile as a function of the change in applied bias.

be given by dV = t x dE = × 

 . Hence, capacitance per unit area due to space charge

distribution of the depletion layer in the reverse bias condition is given as follows [10,23,24,

31, 61-63],

 ≡ 

 =  

 …………………….(27)

In case of forward-biased p-n junction, width of the depletion layer decreases as a

result of high force exerted by electric field acting on charge carriers making them mobile

which induces diffusion capacitance as well [10,23,24]. From the discussion held above, it is

clear that p-n junction acts in form of a condenser in which p- and n-type blocks or layers are

the two plates, while the barrier or depletion layer itself acts as a dielectric. The junction

capacitance is inversely proportional to the thickness of the depletion layer from  = 

 and

measured in Farads. A voltage-controlled capacitance is in which junction capacitance varies

as a function of the applied potential difference. This type of device possessing a variable

reactance is called variable reactor or varactor collectively [10,23,24].

2. Fabrication Technology of Diode

The fabrication technology of a semiconductor p-n junction diode involving different

steps is displayed diagrammatically in Fig. 14 [10,31]. This planar fabrication technology

consists of thermal oxidation of Si wafer to grow SiO2 as the first step (a), second step (b) is

the application of photoresist (PR) over SiO2, third step (c) is the patterning of PR with the

help of optical lithography, fourth step (d) is the etching out of SiO2 and exposing selective

surface of Si wafer, fifth step (e) is removal of the PR, sixth step (f) involves doping of

impurity atoms selectively to produce p-n semiconductor junction, and the last step (g) is the

metallization of the top layer and of the back side for electrical interconnects [10,31]. For the

growth of high quality SiO2, wet or dry thermal oxidation process can be used.

Figure 14. Schematic shows diagrammatically the various steps involved in fabrication

of p-n junction diode. The first step (a) is the thermal oxidation for the growth of SiO2

layer, second step (b) is the application of resist over the grown SiO2 layer, third step (c)

is the patterning of resist, fourth step (d) involves etching out SiO2, fifth step (e) is the

removal of the photoresist. After this, step (f) involves doping of foreign atoms by

diffusion or ion-implantation and step (g) is the metallization step on the top layer and

bottom side of the Si wafer for electrical contacts.

Dry oxidation is performed using dry oxygen for growing thinner oxide layers and

produces high grade features at Si-SiO2 interface. Wet thermal oxidation takes place in

presence of water vapour and is applied to grow thicker oxide layers because of its high

growth rate in comparison to dry thermal oxidation. Growth of high quality pin-hole free

SiO2 layer on Si wafer is an essential requirement in the production and monolithic

integration of integrated circuitry (IC) [10,31]. High-quality SiO2 layer works as device

isolation material which prevents short-circuiting amongst various devices fabricated on a

single Si wafer. It can also be used as a mask to define area covered under the junction in the

fabrication of a semiconductor p-n junction [32-35]. As shown in Fig. 14(b), an organic

photoactive material called photoresist (PR) is applied uniformly over thermally grown

dielectric oxide by a spin-coated at the suitable rounds per minute (rpm) of spinning [36,37].

PR adhesion on the wafer is improved through hardening the resist by evaporation of the

solvent by baking the PR-spun wafer at 80°C - 90°C [31]. Next, the patterned mask is used to

expose the wafer by illumination of UV-light [31]. A patterned mask is an optical mask or

photomask used in optical lithography consisting of pattern of the integrated circuitry or IC.

It is usually a glass substrate coated with the chrome (Cr) and a resist layer [38-40]. The

opaque parts in an optical mask consist of Cr-metal coating responsible for the shadows

casted during exposure of Si wafers. The exposed region of PR-spun wafer or the chemistry

of the PR-spun part that is exposed to the radiation of UV-light changes according to the PR

used as shown in Fig. 14(c). A photoresist can be positive or negative depending on whether

it softens or hardens on exposure to light [36,37,41]. The PR gets polymerized on exposure to

light and it becomes difficult to remove it in an etchant. In the next step, development process

is followed by immersing the wafer in the developer solution [31,42]. Here, unexposed region

or part of the PR-spun wafer that is not exposed to light because of falling under the opaque

part of the optical mask dissolves in the developer solution and is washed away. On the other

hand, the exposed region remains intact in the developer solution and is again baked under

optimized time duration in the temperature range of 120°C-180°C. This not only improves

the adhesion of the exposed part but also makes it robust for the next step of etching process

to remove the oxide selectively. The unmasked oxide layer is removed by an etchant buffered

hydrofluoric (BHF) acid as shown in step (d) of Fig. 14. Finally, the PR is ashed-off by the

physical process of plasma-asher utilizing oxygen (O2) plasma [43,44] or through a chemical

solution as shown in step (e) of Fig. 14. As the last step of fabrication of p-n junction,

diffusion or ion-implantation is performed as per the requirements as shown in step (f) of Fig.

14, and followed by metallization for top and back contacts fabrication (step (g) of Fig. 14).

In step (f), solid-state diffusion process [10,18,31] dopes the opposite type of impurity or

foreign atoms in high concentration into the oxide-layer free part of the relevantly doped

substrate. For example, p-type of foreign atoms are doped in an n-type of substrate and vice-

versa to form p-n junction. As a matter of fact, due to lateral straggle or distribution of

implanted ions or lateral diffusion mechanisms [10,18,31], the width of the doped part is

slightly larger than the unprotected area. Ion-implantation can be performed with a wide

selection of masking materials inclusive of oxide, polysilicon, PRs and metals, low

temperature process, such that, even organic materials like PRs can be used for masking,

excellent lateral uniformity in addition to offering precise control of depth profile and doses

[10,31,45]. After introduction of oppositely-natured impurities in the substrate, top and back-

contacts are deposited by sputtering, e-beam evaporation, thermal evaporation or even

chemical vapour deposition forming the process of metallization [46-50]. This forms ohmic

contacts and interconnects by depositing noble metals that include gold (Au), silver (Au) or

even low cost metals, such as, copper (Cu) and nickel (Ni). Blanket deposition is required for

metallization on the back-side of the wafer. Deposition is usually followed by low-

temperature annealing for promoting adhesion and low-resistance interface between

semiconductor and the metallic layer.

Crystalline silicon solar cell (c-Si) based technology [51-57] has been recognized as the

only environment-friendly viable solution to replace traditional energy sources for power

generation. It is a cost-effective, renewable and long-term sustainable energy source. There

have been constant efforts in reducing manufacturing cost of solar panel technology, which is

about three-four times higher in comparison to traditional carbon-based fuels [58-60]. In the

manufacturing domain, fabrication of three basic c-Si solar cell configurations can be

utilized, which are differentiated in the manner of generation of electron-hole (E-H) pairs on

exposure to sunlight. The three basic c-Si solar cell configurations are monofacial [57,62-64]

bifacial [65-69] and back-contacted [70,71] solar cell configurations as shown in Fig. 15(a),

15(b) & 15(c).

Figure 15(a) shows the schematic of (a) monofacial solar cell, (b) bifacial solar cell and

In the monofacial solar cell configuration as shown in Fig. 15(a), the top point contacts

above the surface of antireflection (AR) film form metallic electrical contacts. On the other

hand, the rear surface consists of completely covering thin metallized layer, which serves as

the second electrode. This is the dominant configuration used in commercial manufacturing

of c-Si solar panel technology. The bifacial solar cell consists of n-doped emitter on both top

and rear sides of the p-type substrate such that both front and back surface metallic grids are

similar as shown in Fig. 15(b). Both top and bottom sides are capable of generating E-H

pairs. The requirement of high efficiency of these solar cells is to have high lifetime of the

minority carriers. In the third type shown in Fi. 15(c), the back-contacted solar cell

configuration, n /p floating junctions are formed on both sides such that p +-doped and n +-

doped regions exist in each of the layers. In this geometry, the top surface does not consist of

any metallic grid. The minority carrier lifetime in these types of solar cells should be high so

that the E-H pairs can diffuse to the back-side of the cell and collectively form external

current. The back-contacted solar cell is the most efficient configuration of commercial solar

cell and its manufacturing requires multiple complicated steps. Fig. 16 shows the various

steps involved in the fabrication of a monofacial solar cell. Similarly, bifacial and back-

contacted solar cells can be fabricated utilizing various growth, patterning and deposition

steps as discussed in general fabrication methodology in Fig. 14 schematically.

Figure 16. Fabrication steps involved in the preparation of a monofacial solar cell.

The generation of electricity by impinging light on a semiconductor material requires

production of electrons and holes such that electrons in the valence band become free and

jump to the conduction band by absorbing energy [72-74]. Thus, jumping of highly energetic

electrons to different material generates an electromotive force (EMF) converting light

energy into electrical signals. This is known as the photovoltaic (PV) effect. The first PV cell

was fabricated by Charles Fritts in 1883 by depositing a thin layer of gold (Au) over the

semiconductor material selenium (Se) to form junctions [72-74]. This firstly fabricated solar

cell was only 1% efficient. A solar cell or PV cell is basically a p -n junction exhibiting

nonlinear current-voltage (I-V) characteristics. Bell laboratories, USA developed first

practical solar cell in 1954 by fabrication of a diffused Si p -n junction with 6% efficiency. Si

is widely used in PV cell technology since it is cheaper, abundant and Si-fabrication

technology is highly developed [72-74]. First of all, polished Si wafers cut from highly pure

industrial grade Si boules are prepared which can be single-crystalline, polycrystalline or

even amorphous. After wafer procurement/fabrication, Si is doped selectively to make p - n

junctions and is processed to furnish a solar cell. The various methods of fabrication of solar

cells are listed as follows [72-74],

(i) Screen printed fabrication technology

(ii) Buried contact fabrication technology

A process flow chart for fabrication of solar cell panels has been shown in Fig. 17. The

Figure 17 shows the process flow for fabrication of solar cells to manufacture

photovoltaic (PV) array. Various steps involved in the fabrication process have been

demonstrated pictorially.

PV technology is based on the photoelectric effect in which a doped semiconductor

produces electricity as a result of electron-hole generation on illumination of solar radiation

[4,5,9,72-74]. The main merits of PV technology include reduced dependency on orthodox

sources of energy of fossil fuels, pollution-free energy technology with zero emission,

significantly reduced operational and maintenance costs, long-life of solar panels of over

twenty years with robust & reliability features. Moreover, system modularity provides the

flexibility of enhancement of power production by simply increasing the number of solar

panels. A solar energy production plant consists of generators or the solar panels and a frame

or hard-casing for mounting the panels in a particular orientation or angle. This is supported

by an electrical power control system and an energy storage system frequently nested in

industries, houses, factories, big farm-houses, universities, colleges, offices and buildings.

The basic component of a PV generator is the solar cell which converts solar radiation into

electrical power.

On illumination of light on the solar cell, E-H pairs arise in both the p- and n-type

regions [4,5,9,72-74]. As discusses previously, an internal electric field is developed due to

the charge carriers in the semiconductor junction. It pushes the extra electrons to segregate

from electronic charge pairing due to the absorption of optical energy and makes them move

in a direction opposite to the movement of holes. This electric field is directed from p-type

region to n-type region, and as a result, electric force prevents them from transportation in the

reverse direction after crossing the electric barrier. For electrical transport, the junction is

interconnected by an external conductor making a closed circuit as shown in Fig. 18. In this

circuit on illumination with light, current flows from n-type block or layer with higher

potential to another n-type block or layer at a lower potential. The saga of electrical

conduction lies in the fact that an electron in the valence band absorbs sufficiently energetic

photon to get excited to the conduction band, a case typical for semiconductor materials with

band-gap energies slightly higher than the metals [4,5,9,72-74].

Figure 18. Schematic shows the electrical contacting of n-type layers with current

flowing from high potential to low layer on illumination of light. The inset shows the

electron jump from valence band (VB) to conduction band (CB) on absorption of

optical energy in form of the quanta of light.

An important fact is that larger the surface area of the solar panel, the larger current is

produced. The genesis is that the region surrounding the p-n junction works as a factory of

charges, while holes and electrons generating in far-flung areas, means away from the

junction, recombine because there is no force supplied by an electric field to drive them off.

This is the main reason for non-conversion of most of the solar energy into electrical energy.

Therefore, the solar energy is responsible for segregation of charge carriers, recombination of

hole-electron charge carriers leading to annihilation, transmission of solar energy, reflection

from the front contacts on surface of the panel in addition to the shadow effects.

Thousands and millions of solar cells fabricated on a solar module are assembled on a

single surface called as the panel. Many panels are assembled or connected in series to form

an array. Several of such arrays are connected in parallel to form the PV generator for

obtaining desired output of electrical power. As a matter of fact, due to subtle manufacturing

defects, the solar cells in the modules are not identical and hence no two blocks connected in

parallel can have the same magnitude of voltage. This results in generation of a current

flowing from cells at higher potential to cell blocks having lower voltages. This creates

mismatch losses due to the fact that a portion of converted power is lost inside the module

itself. Similar problems arise in case of arrays connected in parallel because of dissimilarity

of modules, shadow effects, defects and possessing different irradiance issues. To avoid these

problems, by-pass diodes can be additional electrical components in the non-linear circuitry

to short-circuit the shadowed or maligned part of the module. Mismatch losses due to

dissimilar electrical features of the cells can also be measured by solar irradiances on

shadowed or damaged solar cells. These are cells block the current produced by other solar

cells, are subject to the voltage of other cells and cause local overheating and damages.

Nowadays, crystalline Si solar cells are used with efficiency of 14%-17%, which can be

single crystalline and polycrystalline silicon solar cells [4,5,9,72-74]. These are derived by

chopping-off slices of wafers from the cylindrical ingot. Microgrooves are patterned over and

above the top surface for minimizing losses due to reflection. In polycrystalline silicon

panels, differently oriented silicon crystals based solar cells respond typically on illumination

in case of irradiances and are preferably square-shaped.

Another species of solar cell is based on semiconductor thin films (few µm) deposited on

polymer or glass flexible substrates [75-78]. The thin film materials are inclusive of

amorphous Si [76,79], semiconductor material gallium arsenide (GaAs) [80,81], cadmium-

telluride (CdTe) [82] and copper-indium-gallium-selenide (CIGS) [83,84] alloy materials.

Amorphous Si (a-Si) offers reduced costs than crystalline Si solar cell technology. It is

applied where light-weight solar panels are required and in case of curved surfaces. It

possesses low efficiency and the cell performance also deteriorates with time. An extended

application of a-Si is the tandem solar cell in which amorphous film is coupled with one or

more multi-junction crystalline layers. The variety of tandem solar cells are based on organic

solar cell, inorganic solar cell and hybrid solar cells. Organic solar cells are under intense

research due to significantly low-costs involved but, however, suffer from the problem of

degradation within a short span of one or two weeks generally. CdTeS solar cell consists of

the p-type layer (CdTe) and n-type CdS layer forming a heterojunction solar cell possessing

an efficiency of ~11% in case of industrial grade cells [85,86]. GaAs is next grade

semiconductor material finding many applications in high-speed electronics, space

applications and optoelectronics industry. Alloy based solar materials include copper-indium-

selenide (CIS), copper-indium-gallium-selenide (CIGS) and copper-indium-gallium-selenide-

sulphur (CIGSS) [87]. The two types of PV plants are stand-alone plants and grid based

plants. Stand-alone plants are not connected to the grid and the core structure consists of PV

panels and an energy storage system which ensures electric power supply when sunlight is

not available or poorly available. A PV generator produces direct electric current (DC) power

supply [88-90]. In case, an alternate current (AC) power supply is required to meet the

requirements at the demand end, an inverter for conversion of DC to AC power supply is

required [88-90]. The grid-connected plants fetch electric power from the grid in case of PV

generators are not that much efficient to produce enough power for meeting the clients'

requirements. On production of surplus electric power, the excess can be stored in the grids

and can be used for further utilization. This is not a centralized power technology rather it is a

distributed energy production technology. This offers the advantages of reduced transmission

losses in addition to decreased expenses on electrical transport systems.

3. Energy Production By Equivalent Cell Circuitry

The circuit of a solar cell as a current generator can be represented as shown in Fig. 19.

If the current generated by absorption of photons is I S, diode current is I D and leakage current

is I L, then, the current I obtained at the output terminals is given as follows [88-90],

I = IS – ID - IL …………………….(28)

In the circuit diagram shown below, a series resistance (R S) has been shown which depends

on the thickness of the junction resisting the flow of current across the barrier, types of

impurities and contact resistance. The leakage conductance (G) directly relates to the leakage

current in series under normal conditions of operations. The conversion efficiency of a solar

cell is least affected in a variation of value of G, while a small variation of R S has a

pronounced effect on it. In case of open circuit when no current flows across the load, the

voltage is given as follows,   = 

 …………………….(29)

The diode current I D is expressed by formula for the DC flow and is given as,

 =   ∗ 

  …………………….(30)

where, q is the charge on an electron, T is temperature, k is Boltzmann constant, A is the

identity factor of diode depending on recombination effects inside the diode and I SS is the

saturation current of diode. As a result, current generated across the load is given as follows

from equations (29) & (30) in equation (28),

=  −   ∗ 

  −  …………………….(31)

Figure 19. Schematic shows the electrical circuit of solar cell with current contribution

due to PV effect ( I S), diode current (I D), leakage current (I L), open-circuit voltage (V OC)

when no current flows across the load, leakage conductance ( G) and output current ( I).

It also shows a diode through which I D flows, and series R S offered due to resistance

offered to movement of charge carriers.

Figure 20. Schematic shows the electrical circuit of solar cell with current contribution

due to PV effect ( I S), diode current (I D), leakage current (I L), open-circuit voltage (V OC)

when no current flows across the load, leakage conductance ( G) and output current (I).

It also shows a diode through which I D flows, and series R S offered due to resistance

offered to movement of charge carriers.

The typical current-voltage characteristics of a solar cell module are shown in Fig. 20.

The generated current is the highest (I SC) under short-circuit conditions, whereas it is the least

in case of open-circuit and voltage is the maximum (V OC). The produced electric power in

both these conditions is zero. Under all the conditions other than these two conditions, the

produced power increases as a function of the voltage. Hence, different parameters involved

in the characterization of a solar cell module are the short-circuit current (I SC), open-circuit

voltage (V OC), current and voltages ( I m and V m) produced at the maximum power. The filling

factor (FF) is the ratio of the maximum power (P m) to the product of the open-circuit voltage

(V OC ) multiplied by the short-circuit current (I SC).

Solar panels will display the maximum efficiency when angle of incidence of sunlight is

always perpendicular in a direction to the surface of the panel. The panels must be oriented in

a direction specified by azimuthal angle (γ) which is the deviation in reference to the optimal

direction to the north in the southern hemisphere or with respect to optimum direction in

south in the southern hemisphere [88-90]. Azimuth angle can be defined as the angular

distance determined from north to east along the horizontal line which is the point of

intersection of sphere with the axis.

4. Conclusion

Fabrication of solar cells is based on semiconductor fabrication technology through

which crystalline silicon solar cells are produced at the industrial scale. The conversion

efficiency of industrial-grade silicon solar cells is still around 15%, which is a matter of

concern. This is a costly technology and constant efforts are directed towards developing a

Current (I) in Amperes (A)

Voltage (V)

ISC

Vm V OC

cheaper method with maximized conversion efficiency of the solar cell. An intense research

has been going-on worldwide to develop organic solar cells which is a low-cost process.

Semiconductor manufacturing and subsequent device fabrication is a technology which

requires certain well-defined procedures and protocols, such as, requirement of a clean room.

A clean room is a room with special types of filters attached, for example, HEPA or high

energy particulate filter with purifier) for extraction of smaller particles of 0.3 µm or larger in

size. In certain cases, ultra-low particulate air (ULPA) filters are required when there is need

to extract particles smaller than the aforementioned particles. There are well-defined

protocols to work in these clean room fabrication laboratories or manufacturing facilities. A

special clean room suite or gown is required before entering the laboratory or manufacturing

facility and it is a requirement to pass through the chamber which sucks all smaller particles

before entering the actual laboratory or facility. All the staff entering the clean rooms is

required to qualify a written test and undergo an extensive training before beginning to work

in the laboratory. Moreover, special boots, gloves, teflon-made lab utensils like petry dishes

are required in case of engineers performing etching, oxidation, development processes inside

the clean room. A strategy of monitoring of contaminants, controlling various process

variables and stringent feedback and feed-forward mechanisms ensure defect-free

semiconductor manufacturing. Humidity and temperature control are other factors that are

specifically required and a laminar flow of such controlled air is maintained. This is done to

reduce distribution of contaminants along sideways inside the clean room.

The class of a clean room is determined by the number of particles of a given size

enclosed in a particular volume of air. For illustration, a class 100 clean room consists of not

more than 100 particles of a minimum size of 0.5 µm contained per cubic meter of the

volume of air. Excessive cleanliness is the prerequisite of the industrial grade fabrication

processes due to the fact that introduction of an impurity atom even in parts per million or

parts per billion can lead to manufacturing of a defect-infested device. This leads to the

problems in overall modular or array structure of operation of solar cells and affects

conversion efficiencies. Nowadays, all automated machines are present which perform all

semiconductor manufacturing and processing tasks, such as, etching and ion implantation. No

human interference or involvement is required physically in the clean room and this also

ensures superior manufacturing of devices. However, considering the fact that conversion

efficiencies of solar cells are still not that much high, the costs involved in manufacturing is

bit higher which severely limits its applications. Hence, there has been a surge around the

world to find alternate technology that can produce highly efficient solar cells at a lower cost

of manufacturing. This chapter presents a concise effort to apprise nitty-gritties of

semiconductor physics and fabrication technology in relation to solar cells which is

practically applied at the industrial level. The fabrication steps discussed in the chapter are

actually applicable to various other types of semiconductor based device manufacturing

standards as well.

References

1. Qazi, A., Fayaz, H., Rahim, Abd. N., Hardeker, G., Alghazzawi, D., Shaban, K., and

Haruna, K. (2019). Towards Sustainable Energy : A Systematic Review of Renewable

Energy Sources, Technologies, And Public Opinions. IEEE Access, 7, 63837-63851.

2. Vera G. E. Y., Dufo-Lòpez, R., and Bernal-Agustìn L. J. (2019). Energy Management in

Microgrids With Renewable Energy Sources : A Literature Review. Applied Science, 9,

3854-3882.

3. Archer, D. (2017). Global Warming : Understanding the Forecast – 2 nd Ed., Wiley, pp.1-

214.

4. Parida, B., Iniyan, S., and Goic, R. (2011). A Review of Solar Photovoltaic Technologies.

Renewable and Sustainable Energy Reviews, 15, 1625-1636.

5. Green, A. M. (2019). Photovoltaic Energy And Visions For The Future. Progress in

Energy, 1, 013001(1-14).

6. Viswanathan, B. (2016). Nuclear Fusion in Energy Sources : Fundamentals of Chemical

Conversion Processes and Applications. Elsevier, pp. 127-137, Elsevier.

7. Fiorentini, G., Ricci, B., and Villante, L. F. (2004). Nuclear Fusion In The Sun. Progress

of Theoretical Physics Supplements, 154, 309-316.

8. Maleki, M. A. S., Hizam, H., and Gomes, C. (2017). Estimation of Hourly, Daily And

Monthly Global Solar Radiation On Inclined Surfaces : Models Re-Visited. Energies, 10,

134-162.

9. Buni, B. J. M., Al-Walie, A. K. A., and Al-Asadi, N. A. K. (2018). Effect Of Solar

Radiation On Photovoltaic Cell. International Research Journal of Advanced Engineering

and Science, 3, 47-51.

10. Sze, S. M. (2002). Semiconductor Devices : Physics And Technology – 2nd Ed. Wiley,

pp. 28-30.

11. Kittel, C. (2005). Introduction to Solid State Physics – 8th Ed. , Wiley, pp. 1-703.

12. Hartman, Tomàŝ, and Sofer, Zdeněk (2019). Beyond Graphene : Chemistry of Group 14

Graphene Analogues : Silicene, Germanene, and Stanene. ACS Nano, 13, 8566-8576.

13. Schubert, Fred E. (2003). History of Light-Emitting Diodes, Cambridge University Press,

UK, pp. 1-3.

14. Riordan, M. and Hoddeson, L. (1997). The Origins of The p-n Junction. IEEE Spectrum,

34, 46-51.

15. Lau, S. W. (2017). ULSI Front-End Technology, World Scientific, pp. 1-43.

16. Huff, R. H. (2001). John Bardeen And Transistor Physics. AIP Conference Proceedings,

3, 550-578.

17. Bardeen, J. and Brattain, W. (1948). The Transistor, A Semiconductor Triode. Physical

Review, 74, 230-231.

18. Lécuyer, C. and Brock, C. D. (2006). The Materiality of Microelectronics. Journal of

History and Technology, 22, 301-325.

19. Frosch, J. C. and Derrick, L. (1957). Surface Protection And Selective Masking During

Diffusion In Silicon. Journal of The Electrochemical Society, 104, 547-552.

20. Mahajan, S. and Kimerling, C. L. (1992). Semiconducting Materials & Related

Technologies, Pergamon Press, USA, pp. 15-300.

21. Ayers, E. J. (2007). Heteroepitaxy of Semiconductors : Theory, Growth And

Characterization, CRC Press, Taylor & Francis Group, USA, pp. 1-480.

22. Zhuiykov, S. (2014). Nanostructured Semiconductor Oxides For The Next Generation Of

Electronics And Functional Devices, Woodhead Publishing, USA, pp. 1-466.

23. Smith, P. R., Hwang, A.-C. A., Beetz T. and Helgren, E. (2018). Introduction To

Semiconductor Processing : Fabrication And Characterization of p-n Junction Silicon

Solar Cells. American Journal of Physics, 86, 740-746.

24. Fahey, M. P., Griffin, B. P., and Plummer, D. J. (1989). Point Defects And Dopant

Diffusion In Silicon. Reviews of Modern Physics, 61, 289-384.

25. Macdonald, D. and Geerligs, J. L. (2004). Recombination Activity Of Interstitial Iron

And Other Transition Metal Point Defects In p- And n-type Crystalline Silicon. Applied

Physics Letter, 85, 4061-4063.

26. Mitra, J., Feng, L., Peñate-Quesada, L., & Dawson, P. (2015). An Alternative

Methodology In Schottky Diode Physics. Journal of Applied Physics, 117, 244501(1-10).

27. Waidelich, L. D. (1941). Diode Rectifying Circuits With Capacitance Filters. IEEE

Xplore, 60, 1161-1167.

28. McFee, R. (1971). Self-Rectification In Diodes And The Second Law Of

Thermodynamics. American Journal of Physics, 39, 814-820.

29. Rosdianto, H. (2019). Zener Diode vs. Rectifier Diode : The Comparation of Gaussian

Probability Distribution Function Charts From Full-Wave Rectifier Circuits. IOP

Conference Series : Journal of Physics : Conference Series, 1204, 012003(1-7).

30. Teranishi, N., Fuse, G. and Sugitani, M. (2018). A Review On Ion Implantation

Technology For Image. Sensors, 18, 2358-2375.

31. Sze, M. S. (2003). VLSI Technology. Tata McGraw-Hill Education, pp. 1-662.

32. Gupta, A., Li, W. X., Guha, S., and Xiao, G. (1999). Selective Area And Lateral

Overgrowth Of Chromium Dioxide (CrO2) Films By Chemical Vapour Deposition.

Applied Physics Letters, 75, 2996-2998.

33. Suzuki, K., and Tedrow, M. P. (1998). Selective Deposition Of CrO2 Films On Glass

Substrates. Solid State Communications, 107, 583-585.

34. Razeghi, M. et al. (2009). Semiconductor Device Technology, In : Technology of

Quantum Devices, M. Razeghi, Springer, Boston, USA, pp. 41-82.

35. H. Lin, W. Chen, and F. C. N. Hong. (2013). Improvement of Polycrystalline Silicon

Wafer Solar Cell Efficiency By Forming Nanoscale Pyramids On Wafer Surface Using A

Self-Mask Etching Technique. Journal of Vacuum Science and Technology B, 31,

031401(1-8).

36. Willson, G. C., and Stewart D. M. et al, Photoresists, in : Encyclopedia of Materials :

Science and Technology, K.H. Buschow, M.C. Flemings, E. J. Kramer, Veyssiére, R. W.

Cahn, B. Ilschner and S. Mahajan, pp. 6973-6977, Permagon, Elsevier, 2001.

37. Nakamura, K., Photopolymers : Photoresist materials, processes, and applications (Optics

and photonics book 10), pp. 1-189, 2014.

38. Gupta, S. N., Bagchi, A. K., Nagpal, D. R., and Khokle, W. S., On mask fabrication using

an optical pattern generator in the direct data entry mode. IETE J Res., 29, 457, 1983.

39. Cirelli, A. R., Watson, P. G., and Nalamasu, O., Optical lithography, in : Encyclopedia of

Materials : Science and Technology, K.H. Buschow, M.C. Flemings, E. J. Kramer,

Veyssiére, R. W. Cahn, B. Ilschner, and S. Mahajan, pp. 6973-6977, Pegamon, Elsevier,

USA, 2001.

40. Orabona, E., Calio, A., Rendina, I., Stefano, de L., and Medugno, M., Photomasks

fabrication based on optical reduction for microfluidic applications. Micromachines, 4,

206, 2013.

41. Liao, Y.-Y., and Liu, J.-H., Preparation and characterization of molecular photoresists :

Crosslinkable positive and water developable negative tones. Appl. Poly. Sci., 109, 3849,

2008.

42. Sarangan, A., Nanofabrication, in : Fundamentals and applications of nanophotonics,

Haus, W. J., pp. 1-426, Woodhead Publishing, Elsevier, USA, 2016.

43. Synowicki, R. A., Hale, S. J., McGahan, W. A., Ianno, N. J., and Woollam, J. A., Oxygen

plasma asher contamination : An analysis of sources and remedies. J. Vac. Sci. Technol.

A, 14, 3075, 1996.

44. Bungay, C. L., Tiwald, T. E., DeVries, M. J., Dworak, B. J., and Woollam, J. A., In situ

and ex situ ellipsometric characterization of oxygen plasma and UV radiation effects on

spacecraft materials, MRS Proc., 502, 177, 1997.

45. Licari, J. J., and Enlow, L. R. (1998). Hybrid Microcircuit Technology Handbook :

Materials, Processes, Design, Testing And Production, William Andrew Inc.,USA, pp. 1 -

600.

46. Ziebert, C., Stüber, M., Leiste, H., Ulrich, S., and Holleck, H. (2001). Nanoscale PVD

multilayer coatings, in : Encyclopedia of Materials : Science and Technology, (2001).

K.H. Buschow, M.C. Flemings, E. J. Kramer, Veyssiére, R. W. Cahn, B. Ilschner, and S.

Mahajan, Permagon, Elsevier, pp. 6973-6977.

47. Pezzagna, S. and Meijer, J. (2012). High-Resolution Ion Implantation From keV to MeV,

in : Ion implantation, Goorsky, M., InTech, Croatia, pp. 2 - 24.

48. Yap Y. K. et al. (2012). Physical Vapor Deposition, in: Encyclopedia of

Nanotechnology, Bhushan B. ( Eds.), Springer, Dordrecht, pp. 43 – 59.

49. Martín-Palma, R. J., & Lakhtakia, A. et al. (2013). Vapor-Deposition Techniques, in :

Engineered Biomimicry , Martín-Palma, R. J., Lakhtakia, A, Elsevier, 383 – 398.

50. Baptista, A., Silva, F., Porteiro, J., Míguez, J., and Pinto, G. (2018). Sputtering Physical

Vapour Deposition (PVD) Coatings : A Critical Review On Process Improvement And

Market Trend Demands. Coatings, 8, 402-424.

51. Aberle, A. G. (2001). Overview On SiN Surface Passivation Of Crystalline Silicon Solar

Cells. Solar Energy Materials and Solar Cells, 65, 239-248.

52. Goetzberger, A., Hebling, C., & Schock, H. (2003). Photovoltaic Materials, History,

Status And Outlook. Materials Science and Engineering : R : Reports, 40, 1-46.

53. Sylvester, H., Hakan, H., Johan, N., & Bjorn, K. (2008). Angular Characterization of Low

Concentrating PV-CPC Using Low-Cost Reflectors. Solar Energy Materials and Solar

Cells, 92, 1347-1351.

54. Tobias, I., Cañizo, del C., & Alonso, J. (2011). Crystalline Silicon Solar Cells And

Modules, in : Handbook of Photovoltaic Science and Engineering (2 nd Ed.), A. Luque, S.

Hegedus (Eds.), Wiley, pp. 265 – 313.

55. Iftiquar, S. M., Lee, Y., Ju, M., Balaji, N., Dhungel, S. K., & Yi, J. (2012). Fabrication of

Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and

Screen Printing of Electrode, in : Photodiodes - From Fundamentals to Applications, Ilgu

Yun (Ed.), IntechOpen, pp. 105 - 132.

56. El-Ladan, A.H., Yen, C. H., Ruslan, M.H., Sopian, K., & Zaidi, S. H. (2014).

Comparative Evaluation Of Reflective And Refractive Optical Concentrations Systems In

Tropical Climate. Research Journal of Applied Sciences, Engineering and Technology, 8,

1319-1325.

57. Sopian, K., Cheow, S. L., & Zaidi, S. H. (2017). An Overview Of Crystalline Silicon

Solar Cell Technology : Past, Present, And Future. AIP Conference Proceedings, 1877,

020004, 020004(1-11).

58. Cengiz, M. S., & Mamiş, M. S. (2015). Price-Efficiency Relationship For Photovoltaic

Systems On A Global Basis. International Journal of Photoenergy, 2015, 256101(1-12).

59. Gul, M., Kotak, Y., & Muneer, T. (2016). Review On Recent Trend Of Solar

Photovoltaic Technology. Energy Exploration & Exploitation, 34, 485-526.

60. Cotfas, D. T., and Cotfas, P. A. (2019). Comparative Study of Two Commercial

Photovoltaic Panels Under Natural Sunlight Conditions. International Journal of

Photoenergy, 2019, 8365175(1-12).

61. Ushasree, P. M., and Bora, B. (2019). Silicon solar cells, in : Solar Energy Capture

Materials, E. A. Gibson (Ed.), Royal Society of Chemistry, pp. 1 – 55.

62. Mertens, R. P., Overstraeten, van R. J., & Leuven, K. U. (1984). Solar Cell Fabrication

Techniques For Single And Semicrystalline Silicon Substrates. International Journal of

Solar Energy, 2, 121-140.

63. Iqbal, S., Riaz, K., Imran, H., Khattak, Y. H., Baig, F., & Ahmad, Z. (2020).

Computational Modelling Of Monolithically Stacked Perovskite/Silicon Tandem Solar

Cells Using Monofacial And Bifacial Designs. Optik, 206, 163427(1-13).

64. Amrani, A. E., Mahrane, A., Moussa, F. Y., & Boukennous, Y., Solar Module

Fabrication. International Journal of Photoenergy, 5, 27610(1-6).

65. Guo, S., Walsh, T. M., & Peters, M. (2013). Vertically Mounted Bifacial Photovoltaic

Modules : A Global Analysis. Energy, 61, 447-454.

66. Ooshaksarei, P., Sopian, K. B., & Zulkifli, R. (2013). Characterization Of A Bifacial

Photovoltaic Panel Integrated With External Diffuse And Semimirror Type Reflectors.

International Journal of Photoenergy, 2013, 465837(1-7).

67. Jia, G., Gawlik, A., Plentz, J., & Andrä, G. (2017). Bifacial Multicrystalline Silicon Thin

Film Solar Cells. Solar Energy Materials and Solar Cells, 167, 102-108.

68. Liang, T. S., Pravettoni, M., Deline, C., Stein, J. S., Kopecek, R., Singh, J. P., Luo, W.,

Wang, Y., Aberle, A. G., & Khoo, Y. S. (2019). A Review Of Crystalline Silicon Bifacial

Photovoltaic Performance Characterisation And Simulation. Energy & Environmental Science,

12, 116-148.

69. Lopez-Garica, J., Casado, A., and Sample, T. (2019). Electrical Performance Of Bifacial

Silicon PV Modules Under Different Indoor Mounting Configurations Affecting The

Rear Reflected Irradiance. Solar Energy, 177, 471-482.

70. Desa, M. K. M., Sapeai, S., Azhari, A. W., Sopian, K., Sulaiman, M. Y., Amin, N., &

Zaidi, S. H. (2016). Silicon Back Contact Solar Cell Configuration: A Pathway Towards

Higher Efficiency. Renewable and Sustainable Energy Reviews, 60, 1516-1532.

71. Adhyaksa, G. W. P., Johlin, E., & Garnett, E. C. (2017). Nanoscale Back Contact

Perovskite Solar Cell Design For Improved Tandem Efficiency. Nanoletters, 17, 5206-

5212.

72. Alapatt, G. F., Singh, R., & Poole, K. F. (2012). Fundamental issues in manufacturing

photovoltaic modules beyond the current generation of materials. Advances in

OptoElectronics, 782150, 1-10.

73. Husain, Alaa A. F., Hasan, W. Z. W., Shafie, S., Hamidon, M. N., & Pandey, S. S.

(2018). A Review Of Transparent Solar Photovoltaic Technologies. Renewable and

Sustainable Energy Reviews, 94, 779-791.

74. Luceňo - Sanchez, A. J., Diez-Pascual, M. A., and Capilla, P. R. (2019). Materials For

Photovoltaics : State Of The Art And Recent Developments. International Journal of

Molecular Sciences, 20(4), 976(1-42).

75. Bhatia, S. C. (2014). Solar Photovoltaic Systems, in : Advanced Energy Renewable

Energy Systems, Woodhead Publishing India Pvt. Ltd., pp. 144 – 157.

76. Shah, A. (2017). Thin Film Solar Cells, in : McEvoy's Handbook of Photovoltaics (Third

Edition) : Fundamentals and Applications, S. A. Kalogirou ( Ed. ), Academic Press,

Elsevier Inc., pp. 235 - 307.

77. Szlufcik, J., Sivoththaman, S., Nijs, J. F., & Mertens, R. P., Overstraeten. (2017). Low-

Cost Industrial Technologies For Crystalline Silicon Solar Cells, in : McEvoy's Handbook

of Photovoltaics (Third Edition) : Fundamentals and Applications, S. A. Kalogirou ( Ed. ),

Academic Press, Elsevier Inc., pp. 129 - 158.

78. Sundaram, S., Shanks, K., & Upadhyaya, H. (2018). Thin Film Photovoltaics, in : A

Comprehensive Guide To Solar Energy Systems : With Special Focus on Photovoltaic

Systems, T. M. Letcher and V. M. Fthenakis (Eds.), Academic Press, Elsevier Inc., pp.

361 – 370.

79. Qarony, W., Hossain, M. I., Hossain, M. K., Uddin, M. J., Haque, A., Saad, A. R., &

Tsang, Y. H. (2017). Efficient Amorphous Silicon Solar Cells : Characterization,

Optimization, and Optical Loss Analysis. Results Phys., 7, 4287-4293.

80. Fraas, L. M., Zanio, K. R. & Knechtli, R. C. (1978). Multijunction Gallium Arsenide-

Gallium Arsenide-Germanium Solar Cell And Process For Fabricating Same, US Patent

4,128,733, Hughes Aircraft Company, California, USA, 1-9.

81. Stirn, R. J. (1983). Gallium Arsenide Single Crystal Solar Cell Structure And Method Of

Making, US Patent 4,370,510, assigned to California Institute of Technology, Pasadena,

USA, 1-7.

82. Ferekides, C. S., Balasubramanian, U., Mamazza, R., Viswanathan, V., Zhao, H., &

Morel, D. L. (2004). CdTe Thin Film Solar Cells : Device And Technology Issues. Solar

Energy, 77, 823-830.

83. Ramanujam, J. & Singh, U. P. (2017). Copper Indium Gallium Selenide Based Solar

Cells – A Review. Energy & Environmental Science, 10, 1306-1319.

84. Kim, K.-Bo, Kim, M., Lee, H.-C., Park, S.-W., & Jeon, C.-W. (2017). Copper Indium

Gallium Selenide (CIGS) Solar Cell Devices On Steel Substrates Coated With Thick

SiO2 -Based Insulating Material. Materials Research Bulletin, 85, 168-175.

85. Dharmadasa, I. M., Bingham, P. A., Echendu, O. K., Salim, H. I., Druffel, T.,

Dharmadasa, R., Sumanasekera, G. U., Dharmasena, R. R., Dergacheva, M. B., Mit, K.

A., Urazov, K. A., Bowen, L., Walls, M., & Abbas, A. (2014). Fabrication of CdS/CdTe-

based thin film solar cells using an electrochemical technique. Coatings, 4, 380-415.

86. Kumar, S. G., & Rao, K. S. R. K. (2014). Physics And Chemistry of CdTe/CdS Thin Film

Heterojunction Photovoltaic Devices : Fundamental And Critical Aspects. Energy &

Environmental Science, 7, 45-102.

87. Kim, S. Y., Mina, M. S., Lee, J., & Kim, J. H. (2019). Sulfur-Alloying Effects On

Cu(In,Ga)(S,Se)2 Solar Cell Fabricated Using Aqueous Spray Pyrolysis. ACS Applied

Materials & Interfaces, 11, 45702-45708.

88. Adejuyigbe, S. B., Bolaji, B. O., Olanipekun, M. U., & Adu, M. (2013). Development of

A Solar Photovoltaic Power System To Generate Electricity For Office Appliances.

Engineering Journal, 17, 29-39.

89. Kadhum, J. A., Shneen, S. W., & Hussein, M. A. A. (2018). Utilization of DC Motor-AC

Generator System To Convert The Solar Direct Current Into 220V Alternating Current.

International Journal of Computation and Applied Sciences, 5, 391-396.

90. Nwaigwe, K. N., Mutabilwa, P., & Dintwa, E. (2019). An Overview of Solar Power (PV

Systems) Integration Into Electricity Grids. Materials Science For Energy Technologies,

2, 629-633.

ResearchGate has not been able to resolve any citations for this publication.

Photovoltaic (PV) panels are used for both standalone applications and grid-connected systems. In the former case, the PV panels used vary in size, from very small, for smart solar garden lamps, to standard, in order to ensure the necessary electric energy for a house. For these cases, it is very important to choose the best solution in terms of photovoltaic cell materials. In this paper, a comparative study of two commercial photovoltaic panels, monocrystalline and amorphous silicon, is presented. The two photovoltaic panels are measured in natural conditions, during two years, in Brasov, Romania. The emphasis is placed upon the maximum power generated by the two panels, but the cost and the lifetime are also taken into consideration. The gain in average maximum power for the monocrystalline silicon panel varies from 1.9 times for low irradiance to 2.4 times higher than the one obtained from the amorphous silicon panel, during the test period. The temperature of the monocrystalline silicon panels is lower than that of the amorphous silicon panel in the majority of measurements. The degradation rate determined in two years is 1.02% for the monocrystalline silicon panel and 1.97% for the amorphous silicon panel.

As the efficiency of conventional silicon (Si) solar cell is reaching closer to its thermodynamic limit, its tandem integration with emerging perovskite (PVK) solar cell is being widely explored. In this work, we use self-consistent optical and electrical simulations to computationally explore monolithically stacked 2-terminal (2-T), 2-junction (2-J) PVK/Si tandem solar cell. The optical model is based on Lambert-Beer Law while electrical model is based on drift-diffusion approach. The tandem solar cell is explored for both monofacial and bifacial configurations. The simulations show that the cell design for optimal operations is highly dependent on perovskite thickness and albedo. Under optimal design, the bifacial PVK/Si tandem cell exhibits ∼32.5% for average earth albedo of 30%. Moreover, the cell exhibits a remarkable temperature coefficient of ∼-0.27%. Moreover, our simulation results are in good agreement with both experimental and highly intensive optical model based simulation data. With our computationally inexpensive optical model, the optimal cell design for different tandem structures can be explored in a much easier way.

Renewable energy sources have emerged as an alternative to meet the growing demand for energy, mitigate climate change, and contribute to sustainable development. The integration of these systems is carried out in a distributed manner via microgrid systems; this provides a set of technological solutions that allows information exchange between the consumers and the distributed generation centers, which implies that they need to be managed optimally. Energy management in microgrids is defined as an information and control system that provides the necessary functionality, which ensures that both the generation and distribution systems supply energy at minimal operational costs. This paper presents a literature review of energy management in microgrid systems using renewable energies, along with a comparative analysis of the different optimization objectives, constraints, solution approaches, and simulation tools applied to both the interconnected and isolated microgrids. To manage the intermittent nature of renewable energy, energy storage technology is considered to be an attractive option due to increased technological maturity, energy density, and capability of providing grid services such as frequency response. Finally, future directions on predictive modeling mainly for energy storage systems are also proposed.

A work on the review of integration of solar power into electricity grids is presented. Integration technology has become important due to the world's energy requirements which imposed significant need for different methods by which energy can be produced or integrated, in addition to the fact that integration of solar energy into non-renewable sources is important as it reduces the rates of consuming of non-renewable resources hence reduce dependence of fossil fuels. Photovoltaic or PV system are leading this revolution by utilizing the available power of the sun and transforming it from DC to AC power. Integrating renewable energy of this source into grids has become prominent amongst researchers and scientists due to the current energy demand together with depletion of fossil-fuel reserves and environmental impacts. In this review, current solar-grid integration technologies are identified, benefits of solar-grid integration are highlighted, solar system characteristics for integration and the effects and challenges of integration are discussed. Integration issues and compatibility of both systems (i.e. solar and grid generations) are addressed from both the solar system side and from utility side. This review will help in the implementation of solar-grid integration in new projects without repeating obvious challenges encountered in existing projects, and provide data for researchers and scientists on the viability of solar-grid integration. Keywords: Integration, Solar power, Electricity grid, Grid connections

The use of renewable energy resources such as solar, wind and biomass will not diminish their availability. Sunlight being a constant source of energy is used to meet the ever-increasing energy need. This review discusses the world's energy needs, renewable energy technologies for domestic use, and highlights public opinions on renewable energy. A systematic review of the literature was conducted between the years 2009 to 2018. During this process, more than 300 articles were classified and 42 papers were filtered for critical review. The literature analysis showed that despite serious efforts at all levels to reduce reliance on fossil fuels by promoting renewable energy as its alternative, fossil fuels continue to contribute 73.5% to the worldwide electricity production in 2017. Conversely, renewable sources contributed only 26.5%. Furthermore, this study highlights that lack of public awareness is a major barrier to the acceptance of renewable energy technologies. The results of this study show that worldwide energy crises can be managed by integrating renewable energy sources in the power generation. Moreover, in order to facilitate the development of renewable energy technologies, this systematic review has highlighted the importance of public opinion and performed a real-time analysis of public tweets. This example of tweet analysis is a relatively novel initiative in a review study that will seek to direct the attention of future researchers and policymakers towards public opinion and recommend the implications to both academia and industries.

Haris Rosdianto

The aim of this research is to get an explanation why the use of zener diode in full-wave rectifier circuit is not suitable. The diode used in this research is IN4728 zener diode and IN4002 rectifier diode, which is connected to 1,200 ohm resistor. The circuit is supplied with 5-volt AC power supply with frequency of 50 Hz. The output voltage data of the diode is clipped by using LoggerPro voltage sensor. The data is processed by fitting the data according to the Gaussian probability distribution. The results showed that the Gaussian probability distribution chart of the circuit using IN4728 zener diode has an asymmetric shape, unlike the Gaussian probability distribution chart of the circuit using an IN4002 rectifier diode that has a symmetrical shape. The IN4728 zener diode has breakdown voltage of 3.3 V. When reversed bias is occur and the source voltage exceeds the breakdown voltage of the zener diode, the voltage still pass through the zener diode at 3.3 V. This causes the charts of its Gaussian probability distribution has an asymmetric shape. So it can be concluded that the use of IN4728 zener diode for rectifier circuit is not suitable.

We fabricated Cu(In,Ga)(S,Se)2 (CIGSSe) solar cells by using aqueous spray based deposition, which is low-cost and advantages in large area deposition. To apply the sprayed film to photo-absorber of solar cell, post sulfo-selenization was carried out. Through the sulfo-selenization process, we were able to fabricate various S-alloyed CIGSSe films from S/(S+Se)=0 (S-0.0) to S/(S+Se)=0.4 (S-0.4). CIGSSe solar cells were made with the S-alloyed CIGSSe absorbers. Power conversion efficiency of CIGSSe solar cell was found to be increased with S-alloying up to S-0.3, and the best efficiency of 10.89 % was obtained with S-0.3 CIGSSe absorber. Comparison study of S-alloyed CIGSSe solar cells showed that enhanced efficiency in S-0.3 solar cell is due to the increased open circuit voltage and improved fill factor, which is induced by S-alloying. In addition, admittance spectroscopy revealed that defect density of deep level was developed in the S-alloyed S-0.3 CIGSSe absorber. But defect density was observed to be rather reduced. Details of characterization and analysis results are discussed in this paper.

Tomas Hartman
Zdenek Sofer

2D materials have been extensively studied over the last two decades as they represent a class of materials with properties applicable in catalysis, sensing, optical devices, nanoelectronics, supercapacitors, and semiconductors. The properties of 2D materials can be tuned by exfoliation into mono- or few-layered systems and mainly by surface modification, which can result, for example, in altering the band gap or enhancing material stability toward degradation. This review focuses on the derivatization of Group 14 layered materials beyond graphene silicene, germanene, and stanene and summarizes their preparation as well as chemical and physical properties. This review provides the current state-of-the-art in the field and provides a perspective for future development in the field of chemical derivatization of 2D materials beyond graphene.